1. Field of the Invention
The present invention relates to a semiconductor integrated circuit with a built-in self testing circuit and a method of testing the same.
2. Description of the Prior Art
With increasing integration of random access memories (RAMs), microprocessor units (MPUs), etc., a longer time is needed to test the proper operation of memory cells and logic in the RAMs and the MPUs, resulting in an increase in the test cost involved. One approach to the resolution of this problem is a built-in self testing (BIST) technique which provides the device itself with a test function.
A prior art example of a semiconductor integrated circuit with a built-in self testing circuit is described in Technical Report No. ICD-39 published by the institute of Electronics, Information and Communication Engineers.
FIG. 8 is a block diagram showing the construction of a prior art example of a semiconductor integrated circuit with a built-in self testing circuit. The semiconductor integrated circuit comprises: a main circuit 1 having the intended functions as the semiconductor integrated circuit; a self testing circuit 2 for self testing the main circuit 1; and a test start signal detection circuit 3 that detects the initiation of a test mode by an electrical signal applied from an external terminal through a needle-tipped probe or the like to activate the self testing circuit 2.
In the prior art semiconductor integrated circuit of the above construction, when a prescribed electrical signal is applied from outside the semiconductor integrated circuit, the test start signal detection circuit 3 detects the application of the signal and transfers it as a self testing circuit activation signal 10 to the self testing circuit 2. In response, the self testing circuit 2 enters the test mode to initiate the testing of the main circuit 1. When the test is completed, the self testing circuit 2 electrically outputs a test complete signal 11, which indicates the completion of the test, and a test result signal 12, which indicates the test result, to an external circuit (not shown).
In the above prior art construction, in order to test a plurality of semiconductor integrated circuits formed on a single substrate (e.g., a silicon wafer) before cutting apart and fabricating them into separate chips, terminals through which the power supply voltage, the test start signal, the test complete signal, and the test result signal are transferred to each individual semiconductor integrated circuit must be electrically connected to an external test apparatus (e.g., a prober) by means of needle-tipped probes or other leads. These connections are automatically made using an apparatus called an auto prober, but since it is difficult to make connections to all the semiconductor integrated circuits on the same substrate at the same time, it is necessary to divide the substrate into a number of sections for testing even though a self testing circuit is incorporated in each individual semiconductor integrated circuit. As a result, in testing RAMs or MPUs which require wide-ranging, complex testing, the prior art has had the problem that the testing takes an enormous amount of time, and occupying expensive test instruments for an extended period of time.
For example, in the case of a six-inch wafer with a total of 128 semiconductor integrated circuits formed thereon, each measuring 10 mm.times.20 mm, as shown in FIG. 9, if all the semiconductor integrated circuits on the same substrate are to be tested at once by using their respective internal self testing circuits, a total of four probes will be necessary for testing each semiconductor integrated circuit, at least two for the power supply, one for the test start signal and one for the test result output signal, which means a total of 512 probes for the entire substrate. The number of probes further increases as the device size decreases. The number of probes that can be connected at the same time is at most 100 to 300, and it is therefore essential to minimize the number of probes if all the semiconductor integrated circuits on the same substrate are to be tested at the same time.